This invention relates, in general, to voltage level shifting circuits, and more particularly, to a voltage level shifting circuit suitable as an interface circuit between TTL and CMOS circuitry.
Frequently an interface or buffer circuit is needed between transistor-transistor logic (TTL) and complementary metal oxide semiconductor (CMOS) circuits. The interface circuit must be capable of serving as a voltage level shifting circuit since typically the input voltage will be at a different level than the output voltage. As an example, an input logic level "1" voltage may be in the order of 2 volts while a "0" logic input level may be in the order of 0.8 volts when the input is supplied by a TTL circuit. In a CMOS circuit a logic "1" level will approach the power supply value while a logic "0" level will be near the reference or ground level.
In the past, many different circuits have been used as an interface and voltage level shifting circuit. However, typically these voltage level shifting circuits contain many transistors which occupy an undesirably large amount of silicon area. These circuits tend to cause too large of a delay in transmitting data from the input to the output. It is highly desirable to have a voltage level shifting circuit which is small in size, fast in operation, and low in power consumption.
Accordingly, it is an object of the present invention to provide a voltage level shifting circuit which is small in physical size and fast in operation.
Yet another object of the present invention is to provide a TTL to CMOS voltage level shifting circuit which uses CMOS transistors and consumes a relatively small amount of power.